Requests device identification.

Returns an identification string in IEEE 488.2 specified <NR1> format (four fields separated by commas). The fields are <manufacturer>, <model>, <serial #>, <firmware version>.

OUTPUT

N/A

Activates the currently open frequency parameter as CW.

Activates the frequency parameter that is currently open for data entry as CW, switches to CW if not in CW mode.

CW FREQUENCY

N/A

Deselects step attenuator decoupling.

Deselects the step attenuator decoupling function. This returns the MG362x1A to its normal (coupled) leveling mode. In this mode, when the desired power level is set, the correct combination of level and step attenuator setting is determined by the instrument firmware.

POWER LEVELING

AT1, ATT(xx)

Level | Attenuator

Selects ALC step attenuator decoupling.

This function decouples the step attenuator (if equipped) from the ALC system. This permits separate setting the ALC level and step attenuator.

POWER LEVELING

AT0, ATT(xx)

Sets the step attenuator value to xx (times 10 dB).

Permits setting the step attenuator value to xx (times 10 dB) in the ALC step attenuator decoupling mode.

POWER LEVELING

xx: unsigned integer between 00 (0 dB attenuation) and 11 (110 dB attenuation)

Decouples the step attenuator from the ALC system and sets the step attenuator value to 80 dB.

AT0, AT1

Level | Attenuator | Auto Attenuation to On | Attenuation

Sets CW mode at F0 and opens the F0 parameter.

Places the MG362x1A in CW mode at the preset (or previously set) F0 frequency and causes F0 to be output. Also permits setting the F0 parameter. The frequency setting is determined by the frequency range of the particular MG362x1A model.

CW FREQUENCY

Frequency range of the MG362x1A model

GH, MH, KH, HZ

Places the MG362x1A at the preset (or previously set) CW F0 frequency and opens the F0 parameter for data entry. Sets the F0 frequency to 5.5 GHz.

If in swept mode:

Sets CW mode at F1 and opens the F1 parameter.

Places the MG362x1A in CW mode at the preset (or previously set) F1 frequency and causes F1 to be output. Also permits setting the F1 parameter. The frequency setting is determined by the frequency range of the particular MG362x1A model.

CW FREQUENCY

Frequency range of the MG362x1A model

GH, MH, KH, HZ

CF1, ACW

Frequency | F1

Clears the data entry.

DATA ENTRY

Clear Entry Key

Clears all Native status bytes.

STATUS

N/A

Opens the internal pulse delay1 parameter.

PARAMETER ENTRY

See MG362x1A TDS (11410-00928) for clock rates.

SEC, MS, US, NS

Turns on internal pulse trigger delayed by 100 μs.

OD1 (μs)

IP, PMD(x), PTG(x)

Modulation | Pulse (internal) | Arrow Key | Wdth/Dly List. . . | Edit Selected

Turns on the secure mode.

In the secure mode, the front panel display of all frequency, power level, and modulation parameters is disabled. The instrument continues to function normally in all other respects.

MISCELLANEOUS

System | Secure Mode

Turns off the secure mode.

Restores the front panel display of all frequency, power level, and modulation parameters.

MISCELLANEOUS

System | Reset

Inhibits updating of the ESB2 bit 4.

Blocks updating of the Extended Status Byte two bit four (RF Unlocked). This is the default setting because it is normal for the RF to be momentarily unlocked during sweeps and sweep retrace.

STATUS

SB0, SQ0

N/A

Enables RF Unlocked bit update. ESB2 bit 4.

Unblocks updating of the Extended Status Byte bit four (RF Unlocked).

STATUS

C code snippet to enable unlocked SRQ:

OES (outputs value of the three status bytes)

SQ1

Sets output frequency to F1. Opens the F1 parameter.

Permits setting the F1 parameter. The frequency setting is determined by the frequency range of the particular MG362x1A model.

PARAMETER ENTRY

Frequency range of the MG362x1A model

GH, MH, KH, HZ

F1 returns the F1 frequency value (in MHz) to the controller.

Inhibits extended status byte 1 SRQ generation.

Inhibits an SRQ from being generated when the Extended Status Byte one bit is set. This is the default mode.

STATUS

SQ0, FB1

N/A

Enables extended status byte 1 SRQ generation.

Enables an SRQ to be generated when Primary Status Byte bit zero (Extended Status Byte one) is set and SQ1 has been programmed. The Extended Status Byte one bit is set whenever one (or more) of the unmasked status reporting functions in Extended Status Byte one is true. SQ1 enables the SRQ generation function.

STATUS

C code snippet to enable RF locked SRQ:

OSB (output primary status byte)

N/A

Turns on internal pulse modulation.

Disables the external pulse modulation function, if previously programmed.

MODULATION

Modulation | Pulse (internal) | State On

Sets RF output power level to L0. Opens L0 parameter.

Causes the RF output power level to be set to the preset (or previously set) L0 power level. Also permits setting the L0 parameter. The power level setting is determined by the power level range of the particular MG362x1A model.

POWER LEVELING

Power level range of the MG362x1A model

DM (log), VT (linear)

Places the RF output power level at the preset (or previously set) L0 power level and opens the L0 parameter for data entry. Sets the L0 power level to 5 dBm.

OL0 returns the L0 power level (in dBm when in log mode; in mV when in linear mode) to the controller.

LOG, LIN, PU0, PU1, PU2

Level | Level | L0

 

Sets RF output power level to L1. Opens L1 parameter.

Causes the RF output power level to be set to the preset (or previously set) L1 power level. Also permits setting the L1 parameter. The power level setting is determined by the power level range of the particular MG362x1A model.

POWER LEVELING

Power level range of the MG362x1A model

DM (log), VT (linear)

OL1 returns the L1 power level (in dBm when in log mode; in mV when in linear mode) to the controller.

Level | L1

Inhibits lock error SRQ generation.

Inhibits an SRQ from being generated when the Lock Error bit (Primary Status Byte bit three) is set. This is the default mode.

STATUS

N/A

STATUS

 

Enables lock error SRQ generation. Enables Lock Error bit update. Primary byte bit 3.

Enables an SRQ to be generated when Primary Status Byte bit three (Lock Error) is set and SQ1 has been programmed.

Enable an SRQ on lock error.

N/A

Turns off the level offset function.

POWER LEVELING

LO1, LOS

Turns on the level offset function. Can apply a constant offset to the displayed level value.

POWER LEVELING

LO0, LOS

Opens the level offset parameter.

PARAMETER ENTRY

–100dB to 100dB (logarithmic); +xxx mV to xxx mV (linear)

DB (log), VT (linear)

LO0, LO1

Level | Offset | Level Offset

Inhibits updating of the ESB1 bit 3.

Blocks updating of the Extended Status Byte one bit three (RF Locked). This is the default setting.

STATUS

N/A

Enables updating of the ESB1 bit 3.

Unblocks updating of the Extended Status Byte one bit three (RF Locked).

STATUS

C code snippet to enable the RF locked SRQ:

SQ1, MB1, LS0

N/A

Sets the enable mask byte for the primary status byte.

Sets an eight-bit data mask that is used to enable specific bits of the primary status byte. This enables any or all of the bits (except for bit six) in the primary status byte to generate an SRQ using one eight-bit byte. This command can be equivalent to sending FB1, LE1, PE1, SE1, SB1, and UL1.

STATUS

N/A

Sets the enable mask byte for extended status byte 1.

Sets an eight-bit data mask that is used to enable specific bits of the extended status byte one. This enables any or all of the bits in the extended status byte one to generate an SRQ using one eight-bit byte.

STATUS

C code snippet to enable RF locked bit:

N/A

 

 

 

Sets the enable mask byte for extended status byte 2.

Sets an eight-bit data mask that is used to enable specific bits of the extended status byte two. This enables any or all of the bits in the extended status byte two to generate an SRQ using one eight-bit byte.

STATUS

C code snippet to enable the RF unlocked bit:
strcpy(buf, “mb2 ”); buf[3] = 16; snd(source_addr, buf);

N/A

Returns the Extended SRQ Mask bytes (3 binary bytes) to the controller

OUTPUT

MB0, MB1, MB2

N/A

Returns the GPIB Status bytes (3 binary bytes) to the controller.
Returns the contents of the primary status byte and the two extended status bytes to the controller.

OUTPUT

N/A

Returns the internal pulse period value (in ms) to the controller.
Returns the contents of the primary status byte and the two extended status bytes to the
controller.

OUTPUT

N/A

Returns the primary GPIB status byte to the controller.

OUTPUT

N/A

 

Returns the self-test results (6 binary bytes) to the controller. Can apply a constant offset to the displayed level value.

OUTPUT

TST

N/A

Turns off the internal or external pulse modulation function (This is the default mode).

MODULATION

Valid for the MG369xC product series and made available to avoid a syntax error when programming the MG362x1A product.

Valid for the MG369xC product series and made available to avoid a syntax error when programming the MG362x1A product.

Selects the 100 MHz internal pulse clock rate.

MODULATION

Opens the internal pulse delay1 parameter (Same as D1).

PARAMETER ENTRY

See MG362x1A TDS (11410-00928) for clock rates.

SEC, MS, US, NS

Modulation | Pulse (internal) | Wdth/Dly List. . . | Edit Selected

Inhibits parameter range error SRQ generation.

Inhibits an SRQ from being generated when the primary status byte bit four (parameter range error) is set. This is the default mode.

STATUS

N/A

PE1

STATUS

Enables parameter range error SRQ generation.

Enables an SRQ to be generated when primary status byte bit four (parameter range error) is set and SQ1 has been programmed. SQ1 enables the SRQ generation function.

Enables an SRQ on a parameter range error.

N/A

Opens the internal pulse period parameter.

PARAMETER ENTRY

See MG362x1A TDS (11410-00928) for clock rates.

SEC, MS, US, NS

OPP (in μs)

Turns internal pulse on with a period of 500 μs and pulse width of 50 μs.

Modulation | Pulse (internal) | Edit Period

Selects the internal pulse mode.

Disables the internal ΦM function or the external ΦM function in Narrow mode, had either of these modes been previously programmed. If the ΦM function is not installed, this command produces a syntax error.

MODULATION

x: 1 = Single, 2 = Doublet, 3 = Triplet, 4 = Quadruplet

Turns internal pulse on and sets pulse doublet, 10 μs width, 15 μs delay (from start of first pulse), and 10 μs width.

OMD (text)

Modulation | Pulse (internal) | More > | Mode. . . | Select

Selects the internal pulse trigger.

MODULATION

x: 1 = Free Run, 2 = Gated, 3 = Delayed, 4 = Triggered, 5 = Triggered with Delay

N/A

Opens the internal pulse width1 parameter (Same as W1).

PARAMETER ENTRY

See MG362x1A TDS (11410-00928) for clock rates.

SEC, MS, US, NS

W1

Modulation | Pulse (internal) | Wdth/Dly List. . . | Edit Selected

Turns internal pulse on with a single pulse, free run of width 50 μs.

OPW (in μs)

Turns off the RF output.

POWER LEVELING

Output - LED is Off

Turns on the RF output. This is the default mode.

POWER LEVELING

Output - On (LED is green)

Returns the instrument to local (front panel) control.

MISCELLANEOUS

Selects RF to be on at reset.

This is the default mode.

CONFIGURATION

System | Config | RF | Reset State to On

Selects RF to be off at reset.

CONFIGURATION

System | Config | RF | Reset State to Off

Resets the MG362x1A to its default settings.

Sending this command clears the current instrument setup. If this setup is needed for future testing, save it as a stored setup using the command SSN(M1-9) or SAF before sending RST.

Remote settings are not reset, e.g. Remote language, Ethernet settings, GPIB settings are not reset.

MISCELLANEOUS

System | Reset | System Reset - Application Reset

Inhibits extended status byte 2 SRQ generation.

Inhibits an SRQ from being generated when the Extended Status Byte two bit is set. This is the default mode.

STATUS

N/A

Enables extended status byte 2 SRQ generation.

Enables an SRQ to be generated when primary status byte bit seven (extended status byte two) is set and SQ1 has been programmed. The extended status byte two bit is set whenever one (or more) of the unmasked status reporting functions in extended status byte two is true.

STATUS

C code snippet to enable unlocked SRQ:

SQ1, MB2

N/A

Disables the SRQ generation function. This is the default mode.

STATUS

N/A

Enables the SRQ generation function. Enables SRQ generation when a Primary byte bit is set.

This command allow a status reporting function, that is true and enabled, to pull the SRQ line LOW (true) and request service from the controller.

STATUS

N/A

Selects the instrument's external interface language. The double quotes are required and will be returned with the query reply.

"NATIVE" changes the instrument's external interface language to the Anritsu Native language mode. Any commands issued within 1 second of the change may be garbled or lost.

Note: When changing from NATIVE to SCPI interface language, use the command SYST:LANG "SCPI". Do not use the long form of the command, do not use a leading colon (:), and use exactly one space ( ) between the 'G' and the opening double quote ("). Deviations from this exact command may result in a syntax error.

SYST:LANG

SCPI

Starts an instrument self-test.

When a TST command is received, the signal generator performs a self test, then returns a single byte, unterminated. A "P" (for pass) or an "F" (for fail). Extended Status Byte one bit zero is set if self test fails; bit two is set when self test is complete.

SELF TEST

OSR returns the six self test results bytes to the controller.

System | Diagnostics | Self-Test

Inhibits RF unleveled SRQ generation.

Inhibits an SRQ from being generated when the RF Unleveled bit is set. This is the default mode.

STATUS

N/A

Enables RF unleveled SRQ generation. Enables RF Unleveled bit update. Primary byte bit 2.

Enables an SRQ to be generated when Primary Status Byte bit two (RF Unleveled) is set and SQ1 has been programmed.

STATUS

Enables an unleveled SRQ generation.

N/A

Opens the internal pulse width 1 parameter.

PARAMETER ENTRY

See MG362x1A TDS (11410-00928) for clock rates.

SEC, MS, US, NS

Turns internal pulse on with a 50 μs pulse every 100 μs.

OW1 (in μs)

Modulation | Pulse (internal) | Wdth/Dly List. . . | Edit Selected

Turns on the external pulse modulation function. Disables the internal pulse modulation function, if previously programmed.

Turns on the pulse modulation function. If pulse modulation is not installed, this command produces a syntax error.

MODULATION

Modulation | Pulse | On/Off to On