A T3 circuit (also referred to as a DS3 circuit) is formed by multiplexing together 28 T1 signals in a two‑step process. In the first stage of the two‑step process, 4 T1 (DS1) signals are combined to form a T2 (DS2) signal. Overhead bits are interleaved with the user data to enable framing. Stuff bits are also added to each of the T1 signals to compensate for differences in frequency. Seven T2 signals are then combined to form a T3 signal. Overhead bits are interleaved with the T2 data for framing and error detection at the T3 level.

Two methods are used for combining the seven T2 signals. One method is called M13 framing, and the other method is called C‑bit framing.

M13 multiplexers perform bit stuffing when forming the DS2 signals from the DS1 signals. The DS2 signals that are formed in this manner are synchronous to each other, but the M13 framing assumes that the T2 signals are asynchronous and also uses all 21 DS3 C‑bits for bit stuffing control. This second stage of bit stuffing is not strictly necessary.

The second method is called C‑bit framing, and assumes that the T2 signals are synchronous. The C‑bit parity format does not use the DS3‑level C‑bits for bit stuffing control. With C‑bit framing, the bits that were used by M13 framing to control stuffing are instead used for other functions.

With M13 framing, two of the overhead bits (called P‑bits) are used for a parity check. If the parity of the P‑bits does not match the parity of the data, then a P‑bit error is reported. The parity calculation is repeated on each section of the circuit, so P‑bit errors cannot be used to assess the health of the circuit from end to end.

With C‑bit framing, the DS3‑level overhead bits (that were not used for bit stuffing) are used for other functions, including a C‑bit parity check, a Far End Block Error (FEBE) report, and a Far End Alarm and Control (FEAC) channel. The C‑bit parity bits are set at the originating equipment and are not modified by intervening equipment. They therefore provide an end‑to‑end parity check. When the receiving equipment detects a C‑bit parity error, it sends an error report back to the originating equipment in the FEBE channel. The FEAC channel is used to report alarm and status information from the far‑end terminal to the near‑end terminal.

The three C‑bits in subframe 3 of the DS3 signal (which are designated CP‑bits) are used to carry the DS3 path parity information. At the DS3 terminal equipment (TE) transmitter, the CP‑bits are set to the same value as the two P‑bits. Because the CP‑bits will pass through the network unchanged (except in the case of errors), the DS3 TE receiver can determine if an error occurred in an M‑frame by computing the parity based upon the contents of the given M‑frame and then comparing this parity value with the parity received in the CP‑bits in the following M‑frame.

The FEBE function uses the three C‑bits in subframe 4 of the DS3 signal. This is illustrated in the following example (refer to Figure: DS3 Far-End Block Error (FEBE)):

The near‑end terminal equipment (TE) continuously monitors its incoming direction of transmission (west‑bound in Figure: DS3 Far-End Block Error (FEBE)) for the occurrence of a framing or parity error event. Upon detecting a framing or parity error event via the west‑bound CP‑bits, the near‑end TE will count the event as a C‑bit parity error, and indicate (via the east‑bound FEBE bits) to the far‑end TE that an error has occurred. The C‑bit parity error is indicated via the east‑bound FEBE bits by setting the three FEBE bits to “000” in order to indicate the error. The three FEBE bits are set to “111” if no parity error event has occurred. Because the DS3 terminal equipment (TE) monitors both the CP‑bits and FEBE bits (as well as the FEAC channel), the overall performance of the DS3 path can be determined at either end of the path for both directions of transmission.